Logic Probe Portable Edition – A Proteus circuit by Bob Gornal G7DME

Note this article was created with Proteus software http://proteus.soft112.com/  but only given a simulated test with the software. The full article can be seen along with those previously published in the VS on Bob Gornal’s Proteus circuits page.

I am not sure which one of these items will appear in VS first, or even if they ever will. Tthis little tool has been devised to help people who like experimenting with digital devices using one of the classic Sdeck or Udeck breadboard systems.

I have found this tool very useful when working in the virtual world, so why not bring it into the real world for our breadboard experimenters. The tool is designed to offer the experimenter 4 tools to speed up digital breadboard projects:-

  1.  Dual logic output; true and complementary. The output condition can be switched over at the touch of a button.
    2.    Low Frequency clock, running at around 200 Hz.
    3.    Digital readout of current state of the output; L for low or logic 0 & H for high or logic 1.
    4.    Built-in 9v and 5v power source. Although capable of supplying up to 1A, both power sources are current limited to approx 250 mA so they are only suitable for low to medium current projects. This is to conserve battery life.

So let’s get started.

The basic idea is simple enough; all it needs is a power source, button and resistor; see fig 1:-

Basic Logic State Generator



















Fig 1

How It Works

The power is fed to one side of the switch. The other side of the switch connects to a 10k resistor to ground, and an output is taken from the junction of the switch and the resistor. When the switch is in the off position, the output is pulled down via R1 giving us Logic 0. When the switch is in the on position, the supply flows through the switch and puts a positive potential on the output thus giving us Logic 1. Although fig 1 shows you the general idea, an improved version would be to introduce a buffer CD4010 between the switch and the output. This will ensure a clean changeover from logic 0 to logic 1. This version also helps protect your output from supply fluctuations and ripple current, see fig 2:-


An Improved Logic State Generator Incorporating a 4010 line Buffer


Fig 2

It would also be useful if we could give ourselves a second output or a complimentary output as well; many devices need both logic 1 and Not logic 1 (logic 0). We will also add a capacitor across the switch; the delay it introduces will improve the trigger pulse.

The addition of the inverted pulse is especially useful when playing with memory chips and latches (you can see this implication in fig 5), where you will often find that a latch will require both logic 0 to reset or clear memory, and NOT logic 0 (logic 1) to enable the output. This is easily achieved with the introduction of a CD4069 inverter, see Fig 3 and Fig 4 below:-


Comparison Schematics of Logic States


Fig 3



Fig 4

As you can see in Fig 3, when the switch is in the Off position this gives us the following outputs: output is set at logic 0 and its complimentary output is set to NOT logic 0 (logic 1). Now look at Fig 4 with the switch in the On position. This gives us the following outputs: output logic 1 and its complimentary is set to NOT logic 1 (logic 0). You should now have reasonable understanding of how the logic probe works.

Low Frequency Clock

This is a low frequency clock working on or around 200Hz, see Fig 5. The clock is made up of 3 4069 inverters in series, with R1 acting as current limiting to reduce the amount current flowing into the inputs of U2a to U2d, and the timing is made up of R2 and C1,

Low Frequency Clock or Strobe Schematic


Fig 5

Power supply

The PSU has few unusual characteristics, see Fig 6. As the unit is required to supply power to external circuit, I felt it was necessary to incorporate some form of protection. The easiest way to achieve this was to incorporate a diode in each of the output lines; D5, D6 and D7. Unfortunately this introduced a voltage drop on the 5v rail of about 0.4 of a volt, dropping the output from 5v to 4.53v which I felt could cause problems when used with TTL devices. To overcome this, I introduced D8 & D4 on the earthly side of the 7805 this raised the output voltage to 5.65v. Then when I introduced the diode in the supply line. The final output voltage was now 5.17, well within the operating parameters of TTL devices.

You will also notice the introduction of R22 and R23 in series with the external power lines. These were introduced to limit the available current to 250mA so as to protect the battery and PSU output from a short circuit and prolong the life of the battery.


Power Supply Schematic














Fig 6

Display System & How it Works

The next problem was to give some indication of the output state of the device. There are a number of ways to do this but I settled on the more elegant solution of a digital readout showing H for high (logic 1) & L for low (logic 0). This was not as difficult to do as it first sounds, see Fig 8.

The circuit consists of a switch with the supply +5v on the input side of the switch. A capacitor is connected across the switch and a 10k resistor on the output side of the switch is connected to Gnd. This effectively holds the output of the switch to 0 volts or logic 0. On pressing the button, the capacitor discharged into the output, which is taken from the junction 10k resistor and the output tag of the button. This gives a sharp rise in the output current, generating a clean rising pulse (see Fig 9) on the output before settling at +5v or logic 1. The pulse is then fed into the inputs of the 4010 buffer and the 4069 inverter buffer. The output of the 4010 rises +5v giving us logic 1 and the output of the 4069 falls to 0 volts giving logic 0. On releasing the button, the output falls to 0 volts on the output of the 4010 while the output of the 4069 now rises to +5v or logic 1, see Fig 3 and Fig 4 which graphically shows the whole process. Now we have the toggle action we need to switch the display.

The display itself is made up using 2 7465 6 bit latches and a seven segment display. The input of each latch A1 through A6 is hard wired to produce the required output pattern for the seven segment display. In the case of U3, the pattern for L which is programmed on U3 is A1=1 A2=1 A3=1 A4=0 A5=0 A6=0, and H which is programmed on U4 is A1=0 A2=0 A3=1 A4=0 A5=0 A6=0, see fig 7. The seven segment display chosen was common anode, which means that in order to activate a segment the cathodes must be taken low.






























Fig 7

The 7465 tri-state latch was chosen for simplicity. All that is needed is inputs A1 to A6 to be programmed with the desired display pattern and the outputs Y1 To Y6 are connected to the display segments via a 100R resistor. The chip is equipped with just 2 output enable lines which you tie together take the lines Hi and the output is disabled, or take the lines low and the outputs are enabled. Simplicity in itself and of course, as it’s a tri-state device, no special requirements are needed to connect multiple outputs to single display.

In our case we are using 2 devices where the outputs from both devices are connected directly to the seven segment display via 100R current limiting resistors. The output enable lines of U3 are driven by the 4010 buffer which, when active, displays the L for low or logic 0 and the 4069 buffer inverter drives the output enable on U4 which, when active, displays H for High or logic 1. You should now be getting the general idea.

When the button is in its Off state, the output is held low via the 10k resistor. The line is fed to the input of 4010 buffer, which also remains low. The output, if fed to the output enable of U3, enables its output to activate the display.

Meanwhile the input of the 4069 inv buffer is also held low while its output goes high. Its output is fed to the OE of U4 which turns the display off.

If we press the button, the output of the button goes high and passes through to the input 4010. The output of the 4010 is also held high which in turn holds the OE of U3 high, switching off the output. At the same time the input of the 4069 is held high and, because it’s an inverter, its output is held low which in turn holds the OE of U4 low, turning the display on. That completes the on off sequence.


Display Schematic














Fig 8

Trigger pulse generated by B1, C2, R4 and U2A


















Fig 9

The Completed Tool

Below is a schematic of the final tool (see Fig 13) but first we will look at the PCB visualisations; Top silk (Fig 10), Bottom resist (Fig 11), the populated board (Fig 12). I feel this will be a must for any would be experimenters out there:-


Fig 10.




Fig 11.




Fig 12.




Fig 13.
































PCB Board Details

The following images are the actual size of the PCB with full mechanical details:-


Overall Artwork of PCB




Top Silk and Top Copper




Bottom Copper




SMT Mask




Drilling Details





Top Silk



































Well there is not much more to do except to add that I have a bench version of the project in the pipeline that includes some additional facilities. This will be published later in the year.  I hope this project will prove to be not just a challenging project but a very useful tool to add to your armoury when you have completed it.

De Bob (G7DME).

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