Serial Communications – A Proteus circuit by Bob Gornal G7DME

Hi folks, it’s surprising how often one thing leads to another. About a year ago I was playing around with some NOR gates and one in particular caught my attention. It was the 8-input NOR gate. I was perusing the truth table when I noticed that if all the inputs are held high, the output goes low and, if any input is taken low, then the output goes high.

8 Inputs NOR Gate in action


This got me thinking and I started getting the germ of an idea. It occurred to me that this device could be used to make a simple home intruder alarm system.

The basic alarm came together in about an hour but it was a very crude system and I wanted to make something that would be at least as good as any commercially available system, so the project was started. There have been dozens of revisions over the past 12 months trying out new ideas, adding different features and slowly the design started to come together.

When the project started to reach maturity I realised that for many applications 8 zones may not be enough. So to make it more flexible I began exploring the possibility of adding remote stations. This would expand the alarms coverage from 8 local zones up to 64 remote zones by installing up to 8 remote/local units around a complex. Each unit is capable of covering 8 zones within the vicinity of the alarm system and each unit can be accessible by the master control unit so it can read the status of the remote units at any time. This task requires a good communicating system.

After some research it became apparent that some form of serial communications protocol would be the right way to go; RS232, USB etc. I did consider a parallel system but this would require at least 10 lines per unit coming into the controller; that’s a total of 80 lines. This would not only be costly to implement but it would also render a radio solution for linking the various remote stations to the master controller very difficult to implement.

It was now time to take stock of my communication requirements:-

  1.  To be totally independent of the existing clock system used by the alarm (as that only runs at 1 Hz due to display limitations).
    2.    It needed to be fast, as there are 8 stations to pole.
    3.    Simple as possible and have a very high immunity to errors.
    4.    Leave the data on the main controller so it can be read at random.
    5.    Update the information in real time.
    6.    Alert the operator if one of the remote units is tripped.

It was now time to learn some more about how the various communication systems work. Unfortunately it soon became apparent that most systems required a micro-controller of some description. As my system does not use one, I had to find an alternative. Eventually I came across the Synchronous Communication protocol which sends the local clock with the data stream and an optional stop bit. This eliminates the need for sophisticated error correction and clock synchronisation on the receiving end and theoretically has no speed ceiling. According to the literature out their speeds up to 10Ghz can be achieved, although I will be settling on a more sedate pace of about 1 MHz.

From the literature I had ploughed through, I soon learnt the heart of the system was based on shift register technology, something I was not familiar with. So I did some further research to try and get a handle on how these things worked. There were many variaties of these devices; 4 bit, 5 bit, 7 bit, 8 bit, 14 bit, 16 bit, 24 bit, etc.

But the principals involved was easier enough to understand. On the data transmission side, the parallel data is loaded into a series of set-reset data latches. Once the latches were loaded, the data bits are then shifted by the clock 1 bit at a time along the data latches, creating a serial stream of data on the output; see Fig 2.

The receiving end of the data stream uses the same process, but in reverse. Each data latch is loaded in turn from the incoming data stream. When the last bit has been loaded into the final data latch, the data is written to the display buffers ready for reading; see Fig 2.


Fig 2

Now I had a better understanding of how these devices worked, I started looking at what’s available. I was overwhelmed by the choice devices out there. I went back to the literature and very soon realised there were as many variations in synchronous communications design as there were types of shift registers on the market.

After reading through dozens of datasheets, finally I settled on the 74HC165 8-bit shift register because it appeared to be the simplest to implement; see Fig 3.


Fig (3)

The next problem was to design a timing system for the device. I tried a number of approaches with little or no success. Eventually I settled on the 4017 Johnson ripple counter. This appeared to be ideally suited for the task. It has 10 outputs that are addressed in sequence. Bit 0 could be used to generate the Start Bit, SH/LD. The next 8 bits should be left unused to insert the data stream and 9th bit could be used to generate the Stop Bit (RSTR).

Before I started, I thought it would be good idea to copy out the truth table for the 74HC165 & the 4017 so I could then compare the results; see Fig 2.


74HC169 Truth table

Bit No’s        0 1 2 3 4 5 6 7 8 9
Clock             0 1 0 1 0 1 0 1 0 1
SH                1 0 0 0 0 0 0 0 0 0
LD                 0 1 1 1 1 1 1 1 1 1
Data              0 X X X X X X X 0

Fig 2

The next job was to put the circuit together (see Fig 3) and test it.

Fig 3

I then examined the outputs of the 4017 and compare it with the truth table of the 74HC165; see Fig 4

CD4017 Truth Table

Q0    1 0 0 0 0 0 0 0 0 0        Q5    0 0 0 0 0 1 0 0 0 0
Q1    0 1 0 0 0 0 0 0 0 0        Q6    0 0 0 0 0 0 1 0 0 0
Q2    0 0 1 0 0 0 0 0 0 0        Q7    0 0 0 0 0 0 0 1 0 0
Q3    0 0 0 1 0 0 0 0 0 0        Q8    0 0 0 0 0 0 0 0 1 0
Q4    0 0 0 0 1 0 0 0 0 0        Q9    0 0 0 0 0 0 0 0 0 1
Fig 4

Once I had compared the truth tables, I realised it could not work in its current form as Q0 starts at logic 1, not logic 0, and then remains at logic 0 for the rest of the count; the opposite of what I needed.

It occurred to me I may have to abandon the idea and start all over again. So I examined the truth tables for the second time. After a bit of head scratching I realised, as it often is the case, the solution was staring me in the face. All that was needed was to add an inverter to bit Q0. This would allow me to match the truth tables; see Fig 5 & 6. If you examine them closely, you will notice that Q0 at the start of the count is now logic 0 (Load Function). On the first clock cycle Q0 goes High, Logic 1, and remains high for the next 9 clock cycles, SH=1.


Modified CD4017 Truth Table

Bit    0 1 2 3 4 5 6 7 8 9        Bit    0 1 2 3 4 5 6 7 8 9

Q0    0 1 1 1 1 1 1 1 1 1        Q5    0 0 0 0 0 1 0 0 0 0
Q1    0 1 0 0 0 0 0 0 0 0        Q6    0 0 0 0 0 0 1 0 0 0
Q2    0 0 1 0 0 0 0 0 0 0        Q7    0 0 0 0 0 0 0 1 0 0
Q3    0 0 0 1 0 0 0 0 0 0        Q8    0 0 0 0 0 0 0 0 1 0
Q4    0 0 0 0 1 0 0 0 0 0        Q9    0 0 0 0 0 0 0 0 0 1

Fig 5

74HC169 Truth table

Bit No’s        0 1 2 3 4 5 6 7 8 9

Clock        0 1 0 1 0 1 0 1 0 1
SH        1 0 0 0 0 0 0 0 0 0
LD        0 1 1 1 1 1 1 1 1 1
Data        1  x x x x x x x x  1

Fig 6

I put the modified circuit together circuit; see Fig 6.

Fig (7)

I then connected up the scope and examined the results of the new circuit; see
Fig 7. Everything tied up beautifully. It was time to move onto the next stage of our design.
scope6Fig (7)

After experimenting with various serial to parallel shift registers, I finally settled on the CD4094, again for the same reasons I used the 74HC165. It was the easiest one to implement as it had only 4-inputs; Data, Clock, STB and Output Enable. But before I could use the device I needed to see if its truth table is compatible with our timing device, so again I wrote out the truth table and compared it; see Fig 8.

Bit No’s        0 1 2 3 4 5 6 7 8 9

Clock        0 1 0 1 0 1 0 1 0 1
Data out    0 X X X X X X X 0
Strobe        1 1 1 1 1 1 1 1 1 1
Output Enable    0 0 0 0 0 0 0 0 0 0

Fig (8)

Once I had established that there should be no problems, I set about putting the device together; see Fig 9.

Fig (9)

You can see clearly now from Fig 9 how the 3 wire system works. The clock input is taken from the remote unit. This ensures that no matter what happens the decoder will always be in sync with the encoder. Next is the data line which carries the status information from the remote station and finally you have the RSTR. This is also generated at the remote station, although according to the literature RSTR can be generated locally. This bit is used to tell the 4094 the data stream is finished and returns it to its ready state.

How it Works

The RSTR enables the input latches at the start of the read/write cycle by taking the strobe line to logic 0. The data is clocked in for 8 clock periods. On the 9th clock pulse, the strobe line is taken high and the data written from the input latches to the output buffers ready for reading.

The finally we need to be able to read the data at random from the remote stations.In order to do this, we need to store the data on the master control unit. This is achieved by using the 74HC273 D type latch; 1 for each remote station to store the data. This can then be updated in real time and read anytime.

Initially I did have 1 or 2 problems getting the storage buffer working. When I first set it up I used the remote clock to clock the device but found that the data was only available for 1 clock cycle, which was no good for my requirements. I did not want to read it during an update cycle as this would give the wrong information. I needed a way around this problem so I tried using RSTR clock, as that was only high at the end of the update cycle, but that would not work at all. I even tried inverting the signal but it still would not work. It took me some time to realise what was going on. I wonder if you good can see what the problem is? No, the answer is that the RSTR is positive going only and the 74HC273 is a edge triggered device. This means it needs 1 complete clock cycle to write the data to the output buffers; see Fig 10.






Fig (10)

Now can you see the problem the answer is quite straight forward?

If you refer to Fig 10, you can see the solution to the problem. By adding the system clock signal to the RSTR signal with an AND gate you can generate a complete read write cycle which lasts for 1 clock period, after which time the clock line is held low for the next 8 clock periods before the process is started all over again. This allows the data to be available until we need to read it.










Fig (10)

Below is the completed Serial-Parallel decoder; see Fig (11). Well folks that just about wraps up this project. I hope you have enjoyed your trip into the mysterious world of serial data communications with me.

Fig (8)

De Bob G7DME.

For those of you who want to build this project, the Schematics and PCB information is set out below.







Top Silk







Top Copper








Bottom Copper



Schematic Diagram

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